Semiconductor device protective overcoat with enhanced adhesion to polymeric materials and method of fabrication

ABSTRACT

An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in packaging semiconductor devices, and within the passivating film layers, including the following sequence of materials deposited by PECVD processing: a thin film of silicon dioxide, a layer of silicon nitride, oxy-nitride or silicon carbide, and a very thin topmost layer of silicon oxide.

FIELD OF THE INVENTION

[0001] This invention generally relates to a semiconductor device andmore particularly to the protective overcoat on an integrated circuit.

BACKGROUND OF THE INVENTION

[0002] Typically, integrated circuits (IC) are fabricated on asemiconductor substrate, known as a chip, and the most common substratesare made of silicon. The silicon chip is usually assembled into apackage which serves to provide effective enlargement of the distance orpitch between input/output contacts of the chip making it suitable forattachment to a printed circuit board, and to protect the IC frommechanical and environmental damage. Unfortunately, the package intendedto provide that protection sometimes contributes to the device failure.Such is the case with some surface mount packages housing VLSI chips inwhich poor adhesion at the interface between chip and molding compoundhas caused delamination. A rapid increase in vapor pressure at thedelaminated interface, resulting from moisture absorbed by the plastic,and the rapid heat of soldering the package to the printed wiring boardcauses failures manifested as package cracking, bond wire breakage, andother associated stress related failures.

[0003] Recently the semiconductor industry has introduced reducedpackage sizes, such as those with area array format VS more typicalperipheral attach of the input and output (I/O) terminals to a leadframe encapsulated in molded plastic package. These area arrayassemblies are Chip Scale Packages (CSP)), an example of which isillustrated in FIG. 1, wire bonded or flip chip Ball Grid Array (BGA)packages, and Direct Chip attach (DCA) in which the chip is directlyattached to the printed circuit board without use of an intermediatepackage. Often these area array assembles have solder bumps or balls 11connected by reflowing the solder from the input/output (I/O) contactsof the chip to a substrate or to the Printed Circuit (PC) Board, makingboth electrical and mechanical connections. Because the materials of thesilicon chip 10 and the substrates or PC board 12 have differentcoefficients of thermal expansion (CTE), stresses are introduced in thesolder connection between the rigid, lower CTE chip and the morecompliant, higher CTE PC board. Stresses caused by the thermal expansionmismatch occur during solder reflow, and/or as power to the IC is cycledon and off. The stresses frequently result in mechanical failure of oneor more solder joints, and in turn cause electrical failure of theproduct.

[0004] In an attempt to alleviate the solder fatigue failures, and todistribute the thermally induced stresses over a larger area, apolymeric filler or “underfill” encapsulant 15 is introduced in liquidform to surround the solder balls 11, and to fill the cavity between thechip or CSP 10, and the PC board 12. Typically, the underfill isdispensed near the chip edges and flows under the chip and around thesolder balls by capillary action. The “underfill” cures to a rigid formvia time, temperature, of ultraviolet exposure, or some combinationthereof.

[0005] The “underfill” process has a number of drawbacks, including butnot limited to the following: air pockets or voids 16 being entrappedunder the device which can lead to localized stress concentrations, pooradhesion of the underfill to one or more of the surfaces encountered,and a tedious and time consuming process. The viscous underfillcompound, most commonly an epoxy resin with inorganic fillers, isintroduced methodically and slowly in an attempt to overcome voidformation under the chip resulting from poor wetting to the protectiveovercoat on the chip, the substrate surface and/or the solder bumps.

[0006] Adhesion between material surfaces and the effects of poorwetting have long been studied; the controlling factors are recognizedas cleanliness, surface tension, and topography, as well as thechemistry of the adherents.

[0007] The chip passivation or protective overcoat (PO) of choice formany semiconductor chip manufacturers is silicon nitride, primarilybecause it has been shown to provide excellent resistance to ingress ofmobile ions and contaminants. However, silicon nitride does not provideactive sites for adhesion and wetting, and is subject to stress levelswhich can lead to cracking, and delamination. Stresses vary bydeposition techniques, and concerted attempts are made to control theamount of stress, and to provide compressive forces in order to avoiddegradation of the chip performance and reliability.

[0008] Because of these shortcomings in silicon nitride protectiveovercoats, the chip manufacturer is frequently forced to apply apatterned film of polyimide atop the protective overcoat. FIGS. 2a and 2b illustrate a polyimide film 22 on a chip 20. The polyimide film 22 isapplied in an attempt to provide improved adhesion to polymers used insemiconductor packaging, such as molding compounds 26 in a conventionalleaded plastic molded package in FIG. 2b, or to an underfill or pottingcompound in other types of packages. The polyimide 22 is applied andpatterned atop the silicon nitride or other thin film PO (21).

[0009]FIG. 2a provides a more detailed view of the surface topography ofa chip 20 with a polyimide film 22 patterned over the protectiveovercoat 21. With respect to adhesion, the polyimide film may have anegative effect if it is sufficiently thick enough to leave a smooth,planar surface. The thin silicon nitride protective overcoat 21 followsthe contours of the chip circuitry 24, but the thicker polyimide 22softens the contours, making a more level surface; such a smooth surfaceis not ideally suited to optimum adhesion.

[0010] Further, while the elastic modulus of polyimide films is higherthan typical inorganic films, the thick film coupled with higher thermalexpansion does lead to stress on the wafer which can result in warpingand/or delamination. Organic films, such as polyimide have neither thedesirable high thermal stability, nor the greater thermal conductivityof inorganic films.

[0011] Polyimide precursors are applied in liquid form to the surface ofa wafer having previously been prepared with an adhesion promoter, oralternately having such a compound included in the polyimideformulation. The polyimide must then be photopatterned. The polyimideformulation may include a photosensitive agent which allows directpatterning, or if it does not, a separate photoresist step is required.Next the film is cured or cross linked by a thermal process. Not only isthe polyimide a very expensive compound, but the processing is timeconsuming, costly, and may negatively impact yield of good chips on thewafer.

[0012] Accordingly, a need exists in the industry for a reliable, chipprotective overcoat readily wet by, and having good adhesion topolymers, such as molding and underfill compounds, an overcoat whichimparts little stress on the chip circuitry, and one which is costeffective in wafer processing.

SUMMARY OF THE INVENTION

[0013] It is an object of the current invention to provide a reliableand cost effective chip protective overcoat having good adhesion betweenthe layers, as well as good wetting and adhesion to polymeric materialsused in assembly of integrated circuit chips.

[0014] It is an object of this invention to provide a manufacturingmethod for a protective overcoat having enhanced adhesion, and whichutilize existing wafer fabrication equipment and materials.

[0015] It is further an object of this invention to provide a thermallystable chip protective overcoat which imparts only small andcontrollable stresses to the active circuits and metallization on thechip.

[0016] It is an object of the invention to provide a chip protectiveovercoat having excellent diffusion barrier properties.

[0017] It is also an object of the invention to provide an inorganicchip protective overcoat having improved thermal conductivity ascompared to polymeric coatings.

[0018] The objectives of the invention are accomplished by providing aprotective overcoat on an integrated circuit device including thefollowing sequence of materials: a thin film of silicon oxide in therange of 5,000 to 10,000 angstroms thickness over the active circuit andmetallization, a layer of silicon nitride, oxy-nitride or siliconcarbide of about 1,000 to 5,000 angstroms thickness, and a top adhesionlayer of silicon oxide in the range of 500 to 5,000 angstroms thickness.This composite overcoat is fabricated by plasma enhanced chemical vapordeposition onto silicon wafers by changing the gas compositions, andprocess variables in a reactor, but without additional wafer handling.Openings for input/output terminals are photopatterned and etched in thedeposited overcoat layers.

[0019] The first and third layers of silicon dioxide function to controlstresses imparted by the nitride, to provide excellent dielectricproperties, and to allow adhesion both between the overcoat layers, andto polymers used in assembly of semiconductor devices. The second layerof a silicon nitride, carbide, or oxy-nitride film is used as a barrieragainst ingress of mobile ions or contaminants.

[0020] The foregoing and other objects, features and advantages of theinvention will become more apparent from the following detaileddescription of a preferred embodiment of the invention which proceedswith references to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is a Chip Scale Package with underfill encapsulant. (Priorart)

[0022]FIG. 2a illustrates a chip surface having a polyimide adhesionlayer over protective overcoat. (Prior art)

[0023]FIG. 2b is a leaded plastic package housing a semiconductor devicewith polyimide coating. (Prior art)

[0024]FIG. 3 shows the successive protective overcoat layers of currentinvention.

[0025]FIG. 4 illustrates the process flow for the enhanced adhesionprotective overcoat of the current invention.

[0026]FIG. 5 is a flip chip assemblage having enhanced adhesion betweenPO and the underfill material.

[0027]FIG. 6 is a molded semiconductor device of the current invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0028]FIG. 3 provides a cross sectional view of a portion of asemiconductor chip 30 having the protective overcoat structure 31 of thecurrent invention. A number of novel features contribute to a reliable,high performance device having good adhesion both between the multipledielectric layers of the protective overcoat, and to polymeric materialsused in packaging the chip. In FIG. 3, device circuitry including metalinterconnect lines 34, and buried structures 35 are covered by apassivation or protective overcoat (PO) 31 including the following thinfilm layers formed in succession; a film of silicon dioxide 311, asecond dielectric layer 312 of a silicon compound, preferably siliconnitride, or alternately silicon oxy-nitride or carbide, and a very thinfinal or topmost layer of silicon dioxide 313. The layers are patternedwith openings as required for external contact or other devicerequirements (not shown).

[0029] Dielectric material layers usually function to provide electricinsulation between conductive layers, and to protect underlyingstructures of the integrated circuit against contaminants. Additionally,the provision of successive layers ensures protection for the deviceeven when any one of the layers becomes damaged, e.g., by the formationof small cracks. Therefore, it is important that no regions be allowedto have less than perfect adhesion between the overlaid layers.

[0030] The first layer 311 is silicon dioxide in the range of 5,000 to10,000 angstroms thickness. The term silicon dioxide refers to a notstrictly stoichiometric silicon oxide, i.e., Si[x]O[2−x]. This layerserves both to mitigate stresses of the silicon nitride, or second layerof the protective overcoat structure 31, and to provide an excellentdielectric passivation for the device circuitry. The silicon dioxide asboth the first 311 and third 313 layers provide adhesion to the middleor barrier 312 layer. Further, the first layer of silicon dioxideimparts little to no tensile stress on the circuitry or metallization ofthe chip, and serves to decouple stress from the silicon nitride layerto the underlying circuitry.

[0031] In a preferred embodiment, a silicon nitride or barrier layer 312provides excellent protection against mobile ions, moisture and othercontaminants, which in combination with the oxide layers 311, 313 isequal to thicker nitride overcoats of existing technology. In thecurrent invention, a thickness of 1,000 to 5,000 angstroms is adequatefor the barrier or second layer.

[0032] In a second embodiment, the second layer of the protectiveovercoat 312 is a silicon oxy-nitride, and in yet a third embodiment,the second layer is silicon carbide. Oxy-nitrides are preferable inspecific device types where selected light transmission is necessary.Silicon carbide is well known for having very high thermal conductivity,and as a PO layer serves both to spread localized heat generated by thecircuits across the surface of the chip, and to provide a means totransport heat away from the circuits to the outside world. Techniqueshave been developed for providing thin films of silicon carbide whichhave both excellent barrier characteristics, and the stresses arereadily controllable by the deposition parameters.

[0033] The silicon compounds selected for the second or barrier layerrefer not strictly to stoichiometric formulations, but instead tomixtures comprising substantially the stated compound, and the mixtureas understood within the industry.

[0034] The third or topmost oxide layer is key to adhesion of theovercoat to polymeric materials. Only a very thin film of oxide, in therange of 500 to 5,000 angstroms is required to provide active sites foradhesion to the underlying nitride, and to provide an exposed surfacehaving low surface tension and active sites for wetting and adhesion topolymers and oxides of silicon, such as epoxies used in underfill andplastic molding compounds. Oxides of silicon, e.g., Si—O_(x), Si—OH andsilane reaction products in various forms are well recognized by thoseskilled in the art as adhesion promoters for polymers such as epoxiesused in underfill and plastic molding compounds. (U.S. Pat. No.5,795,821 and U.S. Pat. No. 5,418,189.

[0035] As previously noted, controlling factors for wetting and adhesionbetween materials are recognized as cleanliness, surface tension, andtopography, as well as the chemistry of the adherents.

[0036] From FIG. 3, it can be noted that the thin film enhanced adhesionovercoat 31 follows the topography of the underlying circuit structures,thereby providing an exposed surface having an irregular texture. It haslong been recognized that adhesion is enhanced by a rough or texturedsurface, as opposed to a smooth, planar surface.

[0037] A significant advantage of the adhesion enhanced protectiveovercoat is afforded by compatibility of the process with known waferprocessing technology, and automation used throughout the industry.FIGS. 4a through 4 d illustrate the steps for fabrication of an overcoat31, such as that illustrated in FIG. 3. In FIG. 4a a silicon wafer 40having integrated circuits 44 patterned, including the topmost metalinterconnection 45 level are positioned in a plasma enhanced chemicalvapor deposition chamber. Using a standard PETEOS (plasma enhanced tetraethyl ortho silicate) process designated by arrows 401, an oxide film411 in the range of 5,000 to 10,000 angstroms thick is deposited. In amore detailed view in FIG. 4b, the gas source is changed to includesilane and nitrogen and/or ammonia with the PECVD process designated byarrows 402 to deposit a film of silicon nitride 412 in the range of1,000 to 5,000 angstroms thick. The nitrogen sources are removed, and inFIG. 4c a final thin layer of oxide 413 is added using a standard PETEOSprocess 401. The wafer is removed from the chamber, photoresist 403 isapplied and photopatterned to expose bond pads 48 and/or other openingsrequired by the device. The pattern is preferably etched using a gaseousdry etching process 404 to remove the protective overcoat layers fromthe bond pads, and other openings on the device. Alternately, wetetching with buffered hydrofluoric acid is used to etch the PO.

[0038] Fabrication of the second embodiment, a device having protectiveovercoat layers of silicon dioxide, silicon oxy-nitride, and silicondioxide differs from that described above in that oxygen is introducedalong with nitrogen, silane, and ammonia during the deposition processfor the second layer. The processes for silicon oxy-nitride are knownand used throughout the industry, in particular for EPROM devices.Processes for the first and third layers of the overcoat are unchangedfrom that described above.

[0039] Fabrication of protective overcoat of the third embodimentincluding a layer of silicon dioxide, silicon carbide, and silicondioxide differs from the first embodiment in that silane/methane,trimethylsilane, tetramethylsilane, or other organosilane gas is thesource gas, along with Ar or He as a carrier gas, for the second layerof silicon carbide. Again the first and third layers are of silicondioxide using the PETEOS process.

[0040] Each of the processes for deposition and patterning is well knownthroughout the semiconductor industry, and the equipment is widely used.The combined successive processes form a unique PO structure havingenhanced adhesion to polymers used in IC package assembly, as well asgood adhesion between the film layers, and having minimal stresses onthe circuits, thereby providing a strong, low defect, chip passivation.

[0041] Plasma enhanced chemical vapor deposition (PECVD) of successiveovercoat layers eliminates excessive wafer handling by sequentiallydepositing layered films in a single chamber. Processes employing plasmaenhanced chemical vapor deposition provide clean, uncontaminatedsurfaces between the layers as a function of the atmospheric controlwithin the chamber, thus facilitating adhesion between the multiplelayers. Further, PECVD optimizes process cycle time by successivedepositions without handling, and by a single photopatterning step toetch openings.

[0042] The completely inorganic overcoat of the current invention notonly provides device performance advantages of enhanced adhesion topackaging polymers, but also has very high temperature stability, inexcess of 450 degrees C., and has improved thermal conductivity ascompared to existing enhanced surface adhesion PO technology. Inparticular the embodiment having a silicon carbide second or barrierlayer provides good thermal conductivity, and is applicable to highpower circuits.

[0043]FIG. 5 illustrates a flip chip assemblage of the currentinvention. An integrated circuit device 50 having sequentially depositedprotective overcoat of silicon dioxide 511, silicon nitride 512, andsilicon dioxide 513 is attached to a substrate 52 using solder balls 53.A polymeric underfill compound 55 is completely wetted to the oxidesurface 513 of the protective overcoat, and no voids resulting from pooradhesion are present in the underfill.

[0044] An alternate embodiment is illustrated in FIG. 6 in a crosssectional view of a leaded plastic molded package, wherein themultilayer protective overcoat 61 of the current invention has enhancedadhesion to the molding compound 65. This adhesion is particularlyadvantageous at the corners of chip 69 where delamination of the plasticcan cause shearing of the chip metal structures and /or fatigue of thebond wires.

[0045] While the invention has been described in connection with severalpreferred embodiments, it is not intended to limit the scope of theinvention to a particular form set forth, but on the contrary, it isintended to cover alternatives, modifications and equivalents as may beincluded within the spirit and scope of the invention as defined by theappended claims.

What is claimed is:
 1. An integrated circuit having an enhanced adhesionprotective overcoat, said overcoat including the following thin filmlayers: a first layer of silicon dioxide, a second layer a siliconcompound selected from the group consisting of silicon nitride, siliconcarbide, or silicon oxynitride, and a third layer comprising a very thinfilm of silicon dioxide.
 2. An integrated circuit as in claim 1 whereinsaid first layer is in the range of 5,000 to 10,000 angstroms thick. 3.An integrated circuit as in claim 1 wherein said second layer in therange of 1,000 to 5,000 angstroms thick.
 4. An integrated circuit as inclaim 1 wherein said third layer is in the range of 500 to 5,000angstroms thick.
 5. An integrated circuit as in claim 1 wherein saidlayers are deposited by plasma enhanced chemical vapor deposition.
 6. Anintegrated circuit as in claim 1 wherein said third layer has strongadhesion to polymeric materials.
 7. An integrated circuit as in claim 1wherein said overcoat is thermally stable to greater than 450 degrees C.8. An integrated circuit as in claim 1 wherein said protective overcoatis a barrier against ingress of moisture, mobile ions, and othercontaminants.
 9. An integrated circuit as in claim 1 wherein said firstand third oxide layers have strong adhesion to said second dielectriclayer.
 10. A passivating film including the following thin film layers:a first layer of silicon dioxide, a second layer of a silicon compoundselected from the group consisting of silicon nitride, siliconoxy-nitride, or silicon carbide.
 11. A flip chip semiconductor devicehaving a protective overcoat with enhanced adhesion to polymericmaterials including the following layers: an integrated circuit having afirst surface with active circuits and interconnection, a protectiveovercoat deposited and patterned atop said first surface comprising alayer of silicon dioxide, a second dielectric layer comprising a siliconcompound, selected from the group consisting of silicon nitride, siliconcarbide or silicon oxynitride, and a thin layer of silicon dioxide, anunderfill polymer, and a substrate with solder ball contacts.
 12. Asemiconductor device as in claim 11 wherein said device is a BGApackage.
 13. A semiconductor device as in claim 11 wherein said deviceis a CSP.
 14. A leaded surface mount semiconductor device having aprotective overcoat with enhanced adhesion to polymeric materialscomprising; an integrated circuit having a first surface with activecircuits and interconnection and a second surface attached to a leadframe, a protective overcoat deposited and patterned atop said firstsurface, said overcoat comprising a layer of silicon dioxide, a seconddielectric layer comprising a silicon compound selected from the groupconsisting of silicon nitride, silicon carbide or silicon oxy-nitride,and a thin, third layer of silicon dioxide, wire bonds connecting bondpads on the chip to the lead frame, and a molding compound comprising anepoxy polymer encapsulating said integrated circuit chip with enhancedadhesion protective overcoat, bond wires and the inner leads of a leadframe.
 15. A method of forming a semiconductor device having aprotective overcoat with enhanced adhesion both to polymeric materialsused in packaging and between the layers of said overcoat, the methodincludes the following steps: positioning one or more semiconductorwafers including fabricated integrated circuits into a plasma depositionreactor, evacuating the chamber prior to deposition of a silicon dioxidelayer using a PETEOS (plasma enhanced tetraethyl ortho silicate)process, changing gas supply to include a silane, nitrogen and ammonia,using a PECVD (plasma enhanced chemical vapor deposition) processdepositing a layer of silicon nitride, changing the gas supply todeposit a thin film of silicon dioxide using a PETEOS process, applyinga photoresist, photopatterning the bond pads and/or other opening, andetching the openings in the protective overcoat using a dry etchprocess.
 16. A method of forming a semiconductor device having aprotective overcoat with enhanced adhesion both to polymeric materialsused in packaging and between the layers of said overcoat, the methodincludes the following steps: positioning one or more semiconductorwafers with fabricated integrated circuits into a plasma depositionreactor, evacuating the chamber prior to deposition of a silicon dioxidelayer using a PETEOS (plasma enhanced tetraethyl ortho silicate)process, changing gas supply to include a silane, nitrogen, oxygen andammonia, using a PECVD (plasma enhanced chemical vapor deposition)process depositing a layer of silicon oxy-nitride, changing the gassupply to deposit a thin film of silicon dioxide using a PETEOS process,applying a photoresist, photopatterning the bond pads and/or otheropening, and etching the openings in the protective overcoat using a dryetch process.
 17. A method of forming a semiconductor device having aprotective overcoat with enhanced adhesion both to polymeric materialsused in packaging and between the layers of said overcoat, the methodincludes the following steps; evacuating the chamber prior to depositionof a silicon dioxide layer using a PETEOS (plasma enhanced tetraethylortho silicate) process, changing gas supply to include silane/methane,or an organosilane, such as trimethyl or tetramethyl silane, using aPECVD (plasma enhanced chemical vapor deposition) process depositing alayer of silicon carbide, changing the gas supply to deposit a thin filmof silicon dioxide using a PETEOS process, applying a photoresist,photopatterning the bond pads and/or other opening, and etching theopenings in the protective overcoat using a dry etch process.